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Arithmetic and logic unit is at the heart of any digital circuits and the complex operations which requires to be performed nowadays by the modern processor, the demand for sharing the load by many special-purpose processors are increased. The basic parameters of design on which the performance of ALU depends are speed, size and power efficiency of the ALU. It is observed by various researchers that the use of Vedic mathematics for multiplication strikes a difference in the actual process and hence reduces size and power. It is proved by researchers that the use of Urdhva Tiryakbhyam Sutra of Vedic mathematics can be used to build a power-efficient multiplier in the processor
The beauty of Vedic mathematics lies in the fact that it reduces the cumbersome calculations in conventional mathematics in a very much simplified way. The fundamental concept of Vedic Mathematics lies in the natural principles on which the human mind works and is very much interesting for large-scale computations. This is precisely what makes it more relevant in case of some useful use of Computer Science together with Electronics and Communication Engineering. The different areas where these mathematics are found to be effective and efficient are viz., Compiler Design, Multiplier Design, Computing, VLSI implementation and Digital Signal Processing. As the digital world is coming up in a big way and hence the application of Vedic Mathematics is tried by several researchers of Computer Science and Electronics Engineering and found to be useful in the reduction of speed of the digital circuits as well as reducing the size and power consumption. Arithmetic computations are the fundamental concept of any digital circuit and thus the optimization of these units will increase the efficiency of the entire digital system. It was observed that the computational time and steps required may be greatly reduced by applying Vedic Sulabh Sutras to achieve the desired result of computations. It is worth mentioning that several computer architectures and mathematical algorithms have been designed and implemented by several researchers using Sutras of Vedic Mathematics and found to be optimum and simplified.
Digital signal processing is used in Biomedical Engineering to process Biomedical Signals like MRI scans, X-Ray Scans, PET-Positron Emission Tomography, Electrocardiography (ECG), Cellular motion tracking, Laparoscopic scanning, Computerised Tomography (CT) scans, Ultrasound and Nuclear Medicine Imaging. It is the fastest moving technology of this era and it is the technology that is found everywhere in almost all the engineering fields and hence it puts a great challenge to the entire engineering community. The use of Digital signal processing, image processing, and other robust computation need low processing time and as the process of core computation is a multiplication routine and therefore the engineers are always seeking new algorithms and hardware to efficiently implement real-time problems. This is the reason why the signal processing applications need higher arithmetic operations and hence due to the inherent simple Sutras of Vedic Mathematics finding their place in modern-day signal processing and computations.
As compared to traditional multiplication, steps required to solve multiplication by using Vedic sutras are very few and it helps the Engineers to achieve optimized value at a lower time in all levels of digital designs and power consumption. Vedic multipliers are more efficient in terms of area, power, and speed and the use of the multiplication process based on Vedic algorithms are lower than that of microprocessors which result in appreciable savings of processing time.
Binary multiplication using Urdhwa thiryagbhyam
The role of an Arithmetic Logic Unit (ALU) in the computer is a vital operation in any type of calculation and is a combination of a digital circuit that performs arithmetic and bitwise operations on integer binary numbers. It is well known that the Arithmetic and logic unit is at the heart of any digital circuits and the complex operations which requires to be performed nowadays by the modern processor, the demand for sharing the load by many special-purpose processors are increased. The basic parameters of design on which the performance of ALU depends are speed, size and power efficiency of the ALU. It is observed by various researchers that the use of Vedic mathematics for multiplication strikes a difference in the actual process and hence reduces size and power. It is proved by a few researchers that the use of Urdhva Tiryakbhyam Sutra of Vedic mathematics to build a power-efficient multiplier in the coprocessor is well established. The advantages of Vedic multipliers are an increase in speed, decrease in delay, decrease in power consumption and decrease in area occupancy. It is stated that this Vedic coprocessor is more efficient than the conventional one.
So in short it may be concluded that the use of Vedic Mathematics in modern Engineering Applications is the need of the hour. So our people of Computer Science and Electronics Engineering should work on Vedic Mathematics and recover our buried academic resources.
Application of Vedic Mathematics in Digital Signal Processing & Digital Imaging : P Devaraj,www.cosmicmaths.org